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What is a PCB Netlist and Why do You Need It?

Al Wright
Written by Al Wright
Posted on January 16, 2019 at 8:40 AM

Nobody wants to experience the feeling of populating your new printed circuit board (PCB) design and finding out that it is not electrically functional. Most often, the lack of functionality is attributable to a specific production problem or a combination of several different problems. Sometimes, however, the problem is that the Gerber files exported from your PCB CAD program contained an error that went unnoticed because there was no way to verify that the files matched your design intent. You can avoid a good deal of trouble by supplying an IPC-356 format netlist file with your fabrication data package.

Below is a brief overview of some of the things that can go wrong and how a netlist file helps to catch potential problems at the pre-production stage, instead of on your test bench.

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How the Netlist Is Used Before Editing

The netlist file (formatted as IPC-356) is nothing more than an ASCII text file that includes instructions for the PCB CAM software such as net names, pin, and XY locations of start and end points for each net or node. If the customer supplies an IPC-356 netlist then it is read in during the initial Gerber file load.

Example of a PCB Netlist File

Example of a PCB Netlist File as Viewed in any Standard Text Editor


After loading and placing the Gerber layers into a logical sequence from top to bottom, we use our CAM program to assign a type to each layer. Once the layers are defined electrically, we generate a reference netlist, based on Gerber and drill data. The CAM program identifies areas of COLOR as copper, areas of BLACK as absence of copper, and follows the layer to layer interconnections through the plated through holes.

The CAM program then compares your IPC-356 netlist to the Gerber-derived reference netlist. We report any discrepancies to you and resolve them before moving forward. We do request that the designer call out any known anomalies that we may discover (such as intentional shorts) ahead of time on their drawing or in a separate information file. If they are not called out in the other supporting documentation as requested, then we are obliged to stop and resolve such discrepancies before we can proceed.

Possible Causes of Discrepancies

One might think that Gerber files are infallible and since the industry universally adopted RS274X and ODB++ as standard import formats, they are, in fact, nearly so. However, it is still possible for errors to occur.

Features that are incorrectly described in the Gerber file header during importation will change the system’s interpretation of the desired electrical path leading to incorrect nets being defined in the Gerber-derived reference netlist. Corrupted features may include incorrect-sized pads or unfilled polygons. For example, occasionally a self-intersecting polygon will resolve incorrectly (usually because the Gerber file resolution is not fine enough). This can cause the polygon fill to leak through what the CAM program interprets as a keep-out that is not fully closed. What is intended to be a clearance then floods with copper, shorting the hole and the surrounding plane. Exporting your Gerber files with the highest possible resolution (2:6 if possible) or choosing line fill instead of polygons will help you to avoid this issue but supplying a netlist is still recommended.

Operator setup errors can also cause the CAM program to misunderstand what it is looking at. The most common problem is a simple operator error when assigning the layer types immediately after importing the raw files. If a negative plane is assigned as positive, or vice-versa, the CAM system will see the reverse of what it is supposed to see. With copper and absence of copper switched, it will assign connections where there should be none, and we will see what copper areas as clearances should be.

It is best to supply internal layers with positive polarity whenever possible but, again, the best fail-safe is to also supply a netlist. If the operator runs the design netlist against the CAM reference netlist and sees massive shorting or multiple opens, it is a simple matter to review the layer type and polarity assignments, change a few toggle settings, and be back in business. Absent a netlist file, this error may go unnoticed until you perform an in-circuit test on a populated PCBA.

During CAM Editing

The netlist is kept active throughout the CAM session. When the CAM session is complete, we re-check to the netlist to be sure that no electrical shorts or opens have been created during editing. Then we make files for one of two test fixturing methods.

For Electrical Test Fixturing

A Hard test fixture is created by assigning probes to all net end points. Via (non-component) holes are generally omitted, either because they are mid-points on the net or because they are covered by non-conductive mask and will show as false opens if probed. Other mid-points are often omitted (usually because there are a finite number of grid positions available on the tester, so priority must be given to making sure that a probe is assigned to every end point -- mid-point nodes are omitted). With or without mid-points, the continuity test is still 100% valid as it will pick up all short or open circuits if all end points are probed.

For a Flying Probe test or Clamshell hard fixture (two sides with surface mount pads requiring simultaneous continuity test) the board is mounted either between two moving (flying) probes, or between two parallel plates (clamshell) which are loaded with stationary probes before being compressed to contact the PCB in between. For either fixture style, each net is tested by simultaneously probing the top side net end point and the bottom side net end point.

If IPC netlist is not supplied, then we extract a reference netlist from the Gerber and drill data as described at the beginning. In these cases, the Gerber files must be assumed to accurately reflect the electrical requirements and are used for CAM editing checks and electrical test fixturing.

This is not true for netlist testing, which is more like golden board testing where one board is assumed to be good and the others are tested against the golden sample. Although this does supply insurance that the operator will not accidentally create an electrical problem by means of a bad edit, the glaring flaw to the golden netlist method is that if the system-generated netlist contains an error then all your boards will include the same error because there is no way to catch it.


To take the path of least resistance and avoid preventable mistakes, Epec suggests that if your PCB layout software supports the IPC-356 format, you should always take the time to export the file and send it to your fabricator.

Topics: Printed Circuit Boards, Product Design

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