At the conclusion of our webinar, Why High-Tech Multi-Layer PCB Features Add Cost and Processing Time, we had several questions submitted to our presenter, Angie Brown, PCB Product Manager at Epec. We have compiled these questions into a readable format on our blog.
Q&A From Our Live PCB Webinar
Quick Links:
- What is the added time needed for blind and buried vias?
- Can I have different copper weights on the layers?
- What material is used for cavity PCBs and is there a lead time for it?
- What is the quickest lead time on high-technology PCBs?
- What is the best way to keep costs lower?
- Do you test connectivity when using different types of vias (blind and buried)?
- But if you have mix copper layer, the board can suffer sheer and twist.
- Can you make boards with mix material, FR4 in some stacking, but for RF the top must be specific materials due to high frequency?
- What’s the maximum number of layers that you can make and size of the PCB?
- If HASL was the default but you are showing the LF-HASL as an adder, what is the base finish?
- What would you say is a general cost adder if a hole tolerance is specified as +0.05mm -0.0mm?
- What is the maximum EAU quantity to get the best price?
- If routing of small boards adds cost, is there a lower cost option like v-grooving or something else? How do you create a 1"x1" PCB on a panel?
- Panelization will cost more?
- On slide 6, "mixed" copper weights adding cost was noted. What are the specific attributes that would be considered mixed in this case? Is a combination of 1/2oz and 1oz cores considered "mixed"?
- Solder mask per ANSI/IPC-SM-840, Class 3 (SMOBC), color green, both sides 0.0005 inches thick minimum with liquid photo imageable (LPI) solder mask. Resistant to organic acid fluxes, rm a/ra flux per J-STD-004 and no clean fluxes. Solder mask artwork (as supplied) may be modified to increase the overall pad diameters by up to 0.005 inches; modifications must not eliminate mask dams or expose adjacent circuitry. Class 3 is called out here. Is this correct? The PCB meets IPC-4101/26/98 and IPC 6012 Class 2.
Watch the Recording Below:
Question: What is the added time needed for blind and buried vias?
Answer: Because this is a unique process, and as I said, from blind vias go the top or the bottom to a mid-layer and buried are strictly inside of mid-layers, it really depends on how many sets you have. If they go from the top down the bottom side to mid-layers, if they're sets within the inner layers, etc. So, it really depends on if you can minimize the number of sets that you use. If you can keep to one side or the other, that will help it. I can't really tell you the time needed for it because it really depends on how many sets there are.
Question: Can I have different copper weights on the layers?
Answer: The short answer to that is, yes. With internal layers, you can have unbalanced copper from side to side of the core. So, for a 6-layer, you have the top and the bottom, but you have core layers 2 and 3, and core layers 4 and 5. For layer 2, you could have a half-ounce, and layer 3, you could have 1 ounce. That's what we call a mixed copper. So half-ounce on one side, 1 ounce on the other side. The process is a little different for it because you're etching through to the laminate surface at a different rate of speed because you're removing copper from both sides at the core at the same time. So, it can be done on inner layers. We don't recommend unbalanced copper on external layers for that reason. It is more difficult to process that way. So, sticking to the same copper weight on outer layers is best.
Question: What material is used for cavity PCBs and is there a lead time for it?
Answer: So, cavity boards, pretty much any type of core can be used for a cavity board, but not Teflon or PTFE. And if you have to have exposed internal metal, we must use the no or the low reflow prepregs to get the material removed with an acrylic adhesive. So, it's important to know what it is that you expect the cavity to do.
Question: What is the quickest lead time on high-technology PCBs?
Answer: So, again, that is something to be determined by looking at the data set, depending on how many layers it is, how many PCBs it is, what the attributes that we just talked about for the PCB are. We have done pretty much Plain Jane vanilla, 10-layer boards in 3 to 5 days, but we really need to look at the data set to give you the true answer of that on high-tech PCBs.
Question: What is the best way to keep costs lower?
Answer: One of the things that you can look at if you are developing a high technology PCB and you are thinking of using the blind and buried vias, that process there does add time and cost to manufacturing. You may want to use Epec’s free DFM service and talk to an engineer about possibly changing it from say an 8-layer to a 10-layer. So, adding a layer inside of the stack-up is sometimes a lesser cost than doing the blind and buried vias process.
Question: Do you test connectivity when using different types of vias (blind and buried)?
Answer: We 100% electrically test all products all of the time.
Question: But if you have mix copper layer, the board can suffer sheer and twist.
Answer: Mixed or unbalanced copper can be problematic to produce in a normal PCB setting. It is best to balance copper from side to side on cores.
Question: Can you make boards with mix material, FR4 in some stacking, but for RF the top must be specific materials due to high frequency?
Answer: Yes, most of our mixed technology materials are a combination of Rogers and FR4.
Question: What’s the maximum number of layers that you can make and size of the PCB?
Answer: Generally, we see less than 16 layers the most, however, we have produced many parts over16 layers up to 40 layers. This type of PCB is usually a specialty product and has low volumes. Most of our supply chain can support 16” x 22” as the largest PCB, however, we do have a very capable supplier that can manage larger parts when requested we can provide cost.
Question: If HASL was the default but you are showing the LF-HASL as an adder, what is the base finish?
Answer: In this case, if a default did not match the call out on a fabrication drawing, this would be questioned for confirmation of which is required to be used. Customer service should always quote to print, engineering should always question any conflict between the quote/order for resolution.
Question: What would you say is a general cost adder if a hole tolerance is specified as +0.05mm -0.0mm?
Answer: When a tolerance is below IPC standards, it is our intention to question the relief of the tolerance to allow for processing. It would depend on the size of the hole and if it was plated through or non-plated. If there was no relief allowed, we would review not only in engineering but with production as well to see if the part could be produced. With the prior mentioned part of the equation, I cannot place an exact adder on the hole size however 15-20% in most cases should cover press-fit holes.
Question: What is the maximum EAU quantity to get the best price?
Answer: We would need to review the data set to determine the EAU for best cost with scheduled releases. We also have stocking Kanban/blanket programs available. Consult with your sales representative for more information on this program.
Question: If routing of small boards adds cost, is there a lower cost option like v-grooving or something else? How do you create a 1"x1" PCB on a panel?
Answer: Routing of PCBs is a time-consuming process no matter the size of the part. Not all routing is considered excessive. A small quantity order that is considered excessive routing would not have excessive routing cost, where a part like the example shown in the slide ordered at tens of thousands would have a cost adder. Scoring is another option for parts and can come with an additional cost such as jump scoring but is a quicker method to process. It is best to keep your cost lower, during design and layout consult Epec engineering for a free DFM to review manufacturing potential issues and suggest an array or panel layout.
Question: Panelization will cost more?
Answer: Whether you are buying single pieces, adding rails, or framing within an array the base cost is calculated by the square inch of materials being used. For a part less than 2” x 2”, adding the part into an array is best for production and assembly for ease of processing. In some cases, a part that is smaller than 2” x 2” can cost more to process than parts in the array simply due to manufacturing challenges, time to process, and scrap. It is best to keep your cost lower, during design and layout consult Epec engineering for a free DFM to review manufacturing potential issues and suggest an array or panel layout.
Question: On slide 6, "mixed" copper weights adding cost was noted. What are the specific attributes that would be considered mixed in this case? Is a combination of 1/2oz and 1oz cores considered "mixed"?
Answer: When mixing copper weight from one side of a core to the other as you mention this adds cost to materials and time to process. Unbalanced copper is not a common stock product as well and could be tied to additional materials cost as well. It is best to balance the copper to keep your cost lower, during design and layout consult Epec engineering for a free DFM to review manufacturing potential issues.
Question: Solder mask per ANSI/IPC-SM-840, Class 3 (SMOBC), color green, both sides 0.0005 inches thick minimum with liquid photo imageable (LPI) solder mask. Resistant to organic acid fluxes, rm a/ra flux per J-STD-004 and no clean fluxes. Solder mask artwork (as supplied) may be modified to increase the overall pad diameters by up to 0.005 inches; modifications must not eliminate mask dams or expose adjacent circuitry. Class 3 is called out here. Is this correct? The PCB meets IPC-4101/26/98 and IPC 6012 Class 2.
Answer: It is not uncommon for mask application to be called out as Class III while the fabrication of the PCB is called as Class II. The Class III is not commonly used and, in most cases, when it is, it is overkill as a requirement for the part.
